The present invention relates generally to manufacturing and, more particularly, to a method and apparatus for scheduling preventative maintenance activities by incorporating facility and loop optimizations.
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
A semiconductor fabrication facility typically includes numerous processing tools or machines used to fabricate semiconductor devices. The processing machines may include photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, ion implantation tools, and the like. Wafers (or wafer lots) are processed in the tools in a predetermined order and each processing tool modifies the wafers according to a particular operating recipe so that a desired product is formed in or on the wafer. For example, a photolithography stepper may be used to form a patterned layer of photoresist above the wafer. Features in the patterned layer of photoresist correspond to a plurality of features, e.g. gate electrode structures, which will ultimately be formed above the surface of the wafer. When processing of the wafer is complete, the various features formed in or on the wafer, as well as features formed in or on layers that are deposited above the wafer, combined to form the desired product. Exemplary products include processors, memory elements, and the like.
The semiconductor fabrication facility typically also includes metrology tools for collecting data indicative of the physical state of one or more wafers before, during, and/or after processing by the processing tools. Data collected by the metrology tools may be used to characterize the wafer, to detect faults associated with the processing, or to determine the quality of the finished product. For example, a mean critical dimension associated with the various features may be indicative of a performance level of products formed on the wafer and/or the wafer lot. If the wafer state data indicates that the mean critical dimension associated with the feature, (e.g., a gate electrode) is on the lower end of an allowable range for such feature sizes, then this may indicate that the product formed on the wafer may exhibit relatively high performance levels. For example, smaller feature sizes in a processor formed on the wafer may be associated with faster processing speeds. Higher performance products may be sold at a higher price, thereby increasing the profitability of the manufacturing operation.
High-volume manufacturing environments may be used to form the different products concurrently. For example, a single semiconductor fabrication facility may be used to form hundreds of different products including processors of varying processing speeds and/or architectures, memory elements of different types (e.g., EEPROM, flash memory, etc.) and/or sizes (e.g., 64 MB, 128 MB, etc), and the like.
Commonly, processing tools and metrology tools undergo periodic preventative maintenance procedures or calibrations to keep the tools operating efficiently. For example, polishing tools include polishing pads that are periodically conditioned or replaced. Etch tools and deposition tools are periodically cleaned using both in situ cleans or complete disassembly cleans. Steppers are periodically calibrated to maintain alignment accuracy and exposure dose consistency. Metrology tools are also calibrated periodically.
Many of these preventative maintenance (PM) procedures are performed at discrete intervals based on vendor recommendations, past history, and expected degradation rates of consumable items used in the tools. The use of fixed preventative maintenance intervals is not always an effective solution for optimizing tool and line efficiency. If the maintenance activities are performed more often than actually needed, the efficiency of the line and the operation cost of the tool is increased. If maintenance activities are performed less often than needed, product quality and tool reliability may be degraded.
Effective preventative maintenance scheduling is important in a wafer fabrication environment to increase tool availability and decrease future unscheduled down times. These benefits are indirect benefits of the scheduling system, but cannot be easily quantified. The direct outputs of preventative maintenance procedures are productivity loss in the short term.
Typically, mean time between preventative maintenance (MTBPM) values are determined by machine vendors. Scheduling systems may use a warning window based on vendor recommendations for a PM task that allows the PM to be completed at any time within the window without significantly impacting the production line. Fabrication technicians typically adhere strictly to warning windows when performing PM procedures. This approach may be effective when the facility is not running at full capacity and each machine family has enough capacity to handle the wafers in process (WIP) even though some machines in the family may be unavailable. However, when the WIP level is high, performing too many PM procedures may cause the production line to become imbalanced. Moreover, production targets may be missed when the production is volume driven. For example, a fabrication facility may define a minimum number of activities to be finished each shift, day, or week. The situation is further complicated when cluster tools are used, with each chamber potentially having its own PM schedule.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.